diff --git a/__main__.py b/__main__.py index 49777f5263f1d64f45601286dde25fdcc44b22d0..66ccadf76742dc0c49302a9e9acdd5d54485cbc7 100755 --- a/__main__.py +++ b/__main__.py @@ -22,6 +22,9 @@ subparsers = parser.add_subparsers(help='sub-command help', dest="subparser_name parser_asic = subparsers.add_parser('asic', help='ASIC design') parser_asic.add_argument('label', help='LABEL to identify ASIC design') +parser_cce = subparsers.add_parser('cce', help='Charge Collection Efficiency') +parser_cce.add_argument('label', help='LABEL to identify CCE experiment') + parser_draw = subparsers.add_parser('current', help='calculate drift current') parser_draw.add_argument('label', help='LABEL to identify root files') @@ -68,7 +71,7 @@ if len(sys.argv) == 1: kwargs = vars(args) -submodules = ['asic', 'current', 'draw', 'elec', 'field', 'fpga', 'gen_signal', 'particle', 'spaceres', 'tct', 'timeres'] +submodules = ['asic', 'cce', 'current', 'draw', 'elec', 'field', 'fpga', 'gen_signal', 'particle', 'spaceres', 'tct', 'timeres'] submodule = kwargs['subparser_name'] if submodule not in submodules: diff --git a/cce/__init__.py b/cce/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..da8e43679a20be8d1cceae96f3e8d2d07cfd885c --- /dev/null +++ b/cce/__init__.py @@ -0,0 +1,5 @@ +def main(kwargs): + label = kwargs['label'] + if label == 'HPK-Si-LGAD-CCE': + from cce import cce_alpha + cce_alpha.main() \ No newline at end of file diff --git a/elec/cce_alpha.py b/cce/cce_alpha.py similarity index 100% rename from elec/cce_alpha.py rename to cce/cce_alpha.py diff --git a/elec/__init__.py b/elec/__init__.py index 235229be669878d8e472c315ccc9d682519a5e89..935f8c55ed89488db7f35b78c625cf0271dde1c3 100644 --- a/elec/__init__.py +++ b/elec/__init__.py @@ -11,8 +11,5 @@ def main(kwargs): elif label == 'drs4_get_fig': from . import drs4_get_fig drs4_get_fig.main() - elif label == 'HPK-Si-LGAD-CCE': - from . import cce_alpha - cce_alpha.main() else: raise NameError(label) \ No newline at end of file