From 534466cdc99c6393c759b1ee34bd219ee9efd1dc Mon Sep 17 00:00:00 2001
From: fuchenxi <1256257282@qq.com>
Date: Sat, 21 Sep 2024 22:55:20 +0800
Subject: [PATCH] =?UTF-8?q?=E6=8B=86=E5=87=BAcce=E6=A8=A1=E5=9D=97?=
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---
__main__.py | 5 ++++-
cce/__init__.py | 5 +++++
{elec => cce}/cce_alpha.py | 0
elec/__init__.py | 3 ---
4 files changed, 9 insertions(+), 4 deletions(-)
create mode 100644 cce/__init__.py
rename {elec => cce}/cce_alpha.py (100%)
diff --git a/__main__.py b/__main__.py
index 49777f5..66ccadf 100755
--- a/__main__.py
+++ b/__main__.py
@@ -22,6 +22,9 @@ subparsers = parser.add_subparsers(help='sub-command help', dest="subparser_name
parser_asic = subparsers.add_parser('asic', help='ASIC design')
parser_asic.add_argument('label', help='LABEL to identify ASIC design')
+parser_cce = subparsers.add_parser('cce', help='Charge Collection Efficiency')
+parser_cce.add_argument('label', help='LABEL to identify CCE experiment')
+
parser_draw = subparsers.add_parser('current', help='calculate drift current')
parser_draw.add_argument('label', help='LABEL to identify root files')
@@ -68,7 +71,7 @@ if len(sys.argv) == 1:
kwargs = vars(args)
-submodules = ['asic', 'current', 'draw', 'elec', 'field', 'fpga', 'gen_signal', 'particle', 'spaceres', 'tct', 'timeres']
+submodules = ['asic', 'cce', 'current', 'draw', 'elec', 'field', 'fpga', 'gen_signal', 'particle', 'spaceres', 'tct', 'timeres']
submodule = kwargs['subparser_name']
if submodule not in submodules:
diff --git a/cce/__init__.py b/cce/__init__.py
new file mode 100644
index 0000000..da8e436
--- /dev/null
+++ b/cce/__init__.py
@@ -0,0 +1,5 @@
+def main(kwargs):
+ label = kwargs['label']
+ if label == 'HPK-Si-LGAD-CCE':
+ from cce import cce_alpha
+ cce_alpha.main()
\ No newline at end of file
diff --git a/elec/cce_alpha.py b/cce/cce_alpha.py
similarity index 100%
rename from elec/cce_alpha.py
rename to cce/cce_alpha.py
diff --git a/elec/__init__.py b/elec/__init__.py
index 235229b..935f8c5 100644
--- a/elec/__init__.py
+++ b/elec/__init__.py
@@ -11,8 +11,5 @@ def main(kwargs):
elif label == 'drs4_get_fig':
from . import drs4_get_fig
drs4_get_fig.main()
- elif label == 'HPK-Si-LGAD-CCE':
- from . import cce_alpha
- cce_alpha.main()
else:
raise NameError(label)
\ No newline at end of file
--
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